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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, zarlink semiconductor inc. all rights reserved. features ? 4 10/100 mbps auto-n egotiating rmii ports ? 1 10/100 mbps auto-negot iating mii/serial port (port 4) that can be used as a wan uplink or as a 5th port ? external i 2 c eeprom for power-up configuration - default mode allows op eration without external eeprom ? up to 4 port-based vlans ? full wire-speed layer 2 switching on all ports (up to 1.448 m packets per second) ? internal 1 k mac address table - auto address learning - auto address aging ? leading edge qos capabilities provided based on 802.1p and ip tos/ds field - 2 queues per output port - packet scheduling based on weighted round- robin (wrr) and weighted random early detection/drop (wred) - without flow control can drop packets during congestion using wred - 2 levels of packet drop provided ? supports both full/half duplex ports ? supports external parallel port for configuration updates ? port 3 can be used to mi rror traffic from the other 3 ports (0-2) ? provides port-based prioritization of packets on up to 2 ports (0-1) - input ports are defined to be high or low priority - allows explicit identification of ip phone ports ? ports 0 & 1 can be trunked to provide a 200 mbps link to another switch or server ? utilizes a single low-cost external pipelined, syncburst sram (sbram) for buffer memory - 256 k bytes or 512 k bytes (1 chip) ? flow control capabilities - provides back pressure for half duplex - 802.3x flow control for full duplex ? special power-saving mode for inactive ports ? ability to support winsock2.0 and windows2000 smart applications ? transmit delay control capabilities - provides maximum delay guarantee (<1 ms) - supports mixed voice-data networks ? optimized pin-out for easy board layout november 2003 ordering information MDS105al 208 pin pqfp -40 c to +85 c MDS105 unmanaged 5-port 10/100 mbps ethernet switch data sheet figure 1 - system block diagram MDS105 5-port switch chip s s r a m 10/100 phy 10/100 phy quad rmii mii
MDS105 data sheet 2 zarlink semiconductor inc. description the MDS105 is a fully integrated 5 port ethernet s witch designed to support the low-cost requirements of unmanaged switch applications. the MDS105 provides feat ures that are normally not associated with plug-and- play technology, while not requiring an external processor to facilitate their utilization. the MDS105 begins operating immediately at power-up, learning addresses automatically and forwarding packets at full wire-speed to any of its four output ports or the uplink expansion port. the default configuration allows operation witho ut using an external eeprom. with an eeprom to conf igure the device at power-up, however, the MDS105 provid es flexible features: port trunking, port mirroring, port-based vlans, and quality of service (qos) capabilities that are usually associated only with managed switches. the built-in intelligence of the MDS105 allows it to recognize and offer packet prioritization using zarlink?s qos scheme. packets are prioritized based upon their layer 2 vlan priority tag or the layer 3 type-of- service/differentiated services (tos/ds) field. this prio rity can be defined as transmit and/or drop priority. the MDS105 can be used to create a 4 port unmanaged switch with one wan router port by connecting a cpu (arm or mpc 850) to the additional mii port (port 4). the only external components needed are the physical layer transceivers and a single sbram, resu lting in a low total system cost. designed to support the requirements of converging networks, the MDS105 utilizes a power conserving architecture. to further enhance this power management, the chip automatically detects when a switch port is not being utilized, and turns off the logic associated with that port, thereby saving power and reducing the current load on the switch power supply. operating at 66 mhz internally, and with a 66 mhz interface to the external sbram, the MDS105 sustains full wire- speed switching on all 5 ports. the chip is packaged in a small 208 pin plastic quad flat-pak (pqfp) package.
MDS105 data sheet 3 zarlink semiconductor inc. MDS105 physical pinout 184 186 188 190 192 194 196 198 200 202 204 206 208 74 76 78 12 10 8 6 4 2 72 70 68 66 64 62 60 58 56 54 14 32 30 28 26 24 20 18 16 22 34 52 50 48 46 44 40 38 36 42 nc nc nc nc nc vdd nc nc nc nc nc nc vss nc nc nc nc nc nc vss m2_txd[0] m2_txd[1] m2_crs_dv m2_rxd[0] m2_rxd[1] nc nc nc nc nc nc vss(core) nc nc nc nc nc nc vss (core) nc nc nc nc nc nc vss m1_rxd[1] m1_rxd[0] m1_crs_dv m1_txd[1] m1_txd[0] m1_txen vdd m0_rxd[1] m0_rxd[0] m0_crs_dv m0_txd[1] m0_txd[0] m0_txen vss (core) nc nc nc nc nc nc vdd l_a[13] l_a[14] l_a[12] vss l_a[11] l_a[10] l_a[9] vdd_core l_a[8] l_a[7] la_[6] vss l_a[5] l_a[4] l_a[18] l_d[31] l_d[30] l_d[29] vss (core) l_d[28] l_d[27] l_d[26] vdd l_d[25] l_d[24] l_d[23] l_d[22] vss l_d[21] l_d[20] l_d[19] l_d[18] vdd (core) rmii port interfaces 182 180 178 176 174 172 170 168 166 164 162 160 158 84 82 80 146 148 150 152 154 156 86 88 90 92 94 96 98 100 102 104 144 126 128 130 132 134 138 140 142 136 124 106 108 110 112 114 118 120 122 116 m3_txen m3_txd[0] m3_txd[1] m3_crs_dv m3_rxd[0] m3_rxd[1] vdd nc nc nc nc nc nc vss m_clk vdd (core) m4_rxdv m4_col m4_rxclk vdd m4_rxd[0] m4_rxd[1] m4_rxd[2] m4_rxd[3] vss (core) m4_txclk vdd m4_txen m4_txd[0] m4_txd[1] m4_txd[2] m4_txd[3] m4_link m4_duplex m4_refclk vdd m_mdc vss scl test# trunk_en strobe data0 ack vdd (core) tstout[0] tstout[1] tstout[2] tstout[3] tstout[4] tstout[6] tstout[7] t_mode vss(core) rstout# mir_ctl[0] mir_ctl[2] mir_ctl[3] sclk vdd vss l_a[2] l_a[17] vdd l_clk vss l_we# l_d[16] vss l_d[14] l_d[13] l_d[12] l_d[11] vdd l_d[10] l_d[9] l_d[8] vss (core) l_d[7] l_d[6] l_d[5] l_d[4] vdd l_d[3] l_d[1] l_d[0] l_a[15] vdd(core) l_a[16] l_adsc# nc m2_txen vss (core) vdd (core) l_a[3] vdd l_d[17] l_d[15] l_d[2] vss l_oe# mir_ctl[1] rstin# tstout[5] sda m_mdio vss m4_speed buffer mem interface config interfaces rmii port interfaces + pin 1 i.d.
MDS105 data sheet 4 zarlink semiconductor inc. pin reference table pin # pin name 1l_a[7] 2l_a[8] 3vdd (core) 4l_a[9] 5l_a[10] 6 l_a[11] 7 vss 8l_a[12] 9l_a[13] 10 l_a[14] 11 vdd 12 nc 13 nc 14 nc 15 nc 16 nc 17 nc 18 vss (core) 19 m0_txen 20 m0_txd[0] 21 m0_txd[1] 22 m0_crs_dv 23 m0_rxd[0] 24 m0_rxd[1] 25 vdd 26 m1_txen 27 m1_txd[0] 28 m1_txd[1] 29 m1_crs_dv 30 m1_rxd[0] 31 m1_rxd[1] 32 vss 33 nc 34 nc 35 nc 36 nc 37 nc 38 nc 39 vdd (core) 40 nc 41 nc 42 nc 43 nc 44 nc 45 nc 46 vss (core) 47 nc 48 nc 49 nc 50 nc 51 nc 52 nc 53 nc 54 nc 55 nc 56 nc 57 nc 58 nc 59 vdd 60 nc 61 nc 62 nc 63 nc 64 nc 65 nc 66 vss 67 nc 68 nc 69 nc 70 nc 71 m5_rxd[0] 72 m5_rxd[1] 73 vdd (core) 74 m6_txen 75 m6_txd[0] 76 m6_txd[1] 77 m6_crs_dv 78 m6_rxd[0]] 79 m6_rxd[1] 80 vss (core) 81 m7_txen 82 m7_txd[0] 83 m7_txd[1] 84 m7_crs_dv 85 m7_rxd[0] 86 m7_rxd[1] 87 vdd 88 nc 89 nc 90 nc 91 nc 92 nc 93 nc 94 vss 95 m_clk 96 vdd (core) 97 m8_rxdv/s8_crs_dv 98 m8_col/s8_col 99 vss 100 m8_rxclk/s8_rxclk 101 vdd 102 m8_rxd[0]/s8_rxd 103 m8_rxd[1] 104 m8_rxd[2] 105 m4_rxd[3] 106 vss (core)
MDS105 data sheet 5 zarlink semiconductor inc. 107 m8_txclk/s8_txclk 108 vdd 109 m8_txen[0]/s8_txen 110 m8_txd[0]/s8_txd 111 m8_txd[1] 112 m8_txd[2] 113 m8_txd[3] 114 m8_link/s8_link 115 m8_duplex/s8_dupl ex 116 m8_speed 117 vss 118 m8_refclk 119 vdd 120 m_mdc 121 vss 122 m_mdio 123 scl 124 sda 125 test# 126 trunk_enable 127 strobe 128 data0 129 ack 130 vdd (core) 131 tstout[0] 132 tstout[1] 133 tstout[2] 134 tstout[3] 135 tstout[4] 136 tstout[5] 137 tstout[6] 138 tstout[7] 139 t_mode 140 vss (core) 141 rstout# 142 rstin# 143 mirror_control[0] 144 mirror_control[1] 145 mirror_control[2] 146 mirror_control[3] 147 vdd 148 sclk 149 vss 150 l_a[2] 151 l_a[17] 152 vdd 153 l_clk 154 vss 155 l_we# 156 l_oe# 157 l_adsc# 158 l_a[16] 159 vdd (core) 160 l_a[15] 161 l_d[0] 162 vss 163 l_d[1] 164 l_d[2] 165 l_d[3] 166 vdd 167 l_d[4] 168 l_d[5] 169 l_d[6] 170 l_d[7] 171 vss (core) 172 l_d[8] 173 l_d[9] 174 l_d[10] 175 vdd 176 l_d[11] 177 l_d[12] 178 l_d[13] 179 l_d[14] 180 vss 181 l_d[15] 182 l_d[16] 183 l_d[17] 184 vdd (core) 185 l_d[18] 186 l_d[19] 187 l_d[20] 188 l_d[21] 189 vss 190 l_d[22] 191 l_d[23] 192 l_d[24] 193 l_d[25] 194 vdd 195 l_d[26] 196 l_d[27] 197 l_d[28] 198 vss (core) 199 l_d[29] 200 l_d[30] 201 l_d[31] 202 vdd 203 l_a[18] 204 l_a[3] 205 l_a[4] 206 l_a[5] 207 vss 208 l_a[6]
MDS105 data sheet 6 zarlink semiconductor inc. MDS105 block diagram figure 2 - MDS105 block diagram
MDS105 data sheet 7 zarlink semiconductor inc. 1.0 functional operation the MDS105 is designed to provide a cost effective layer 2 switching solution, using technology from the zarlink family to offer a highly integrated product for the unmana ged, differentiated services (ds) ready, ethernet switch market. five 10/100 media access controllers (mac) provide the protocol interface. these macs perform the required packet checks to ensure that each packet that is provided to the frame engine has met all the ieee 802.1 standards. each mac supports half duplex ?back pressure,? and full duplex 802.3x ?pause? flow control. the phy addresses for the 4 rmii macs are from 08h to 0b h. these four ports are denoted as ports 0 to 3. the phy address for the uplink mac is 10 h. this port is denoted as port 4. data packets longer than 1518 (1522 with vlan tag) bytes and shorter than 64 bytes are dropped, and the MDS105 is designed to support minimum interframe gaps between incoming packets. the frame engine (fe) is the primary packet buffering a nd forwarding engine within the MDS105. as such, the fe controls the storage of packets into and out of the ex ternal frame buffer memory, keeps track of frame buffer availability, and schedules packet transmissions. while packet data is being buffered, the fe extracts the necessary information from each packet header and sends it to the search engine for processing. search results returned to the fe initiate the scheduling of packet transmission. wh en a packet is chosen for transmission, the fe reads the packet from external buffer memory and places it in the output fifo of the output port. 2.0 address l earning and aging the MDS105 is able to begin address learning and packet forwarding shortly after power up is completed. the search engine examines the contents of its internal switch database memory for each valid packet that is received on a MDS105 input port. unknown source and destination mac addresses are dete cted when the search engine does not find a match within its database. these unknown source mac addresses are learned by creating a new entry in the switch database memory, and storing the necessary resulting info rmation in that location. subsequent searches to a learned destination mac address will return the new contents of that mac c ontrol table (mct) entry. after each source address search the mct entry aging fl ag is updated. mct entries that have not been accessed during a user configurable time period (1 to 67,108 se conds) will be removed. this aging time period can be configured using the 16 bit value stored in the registers mac address aging timer low and high (agetime_low, agetime_high). the aging period is defined as the bit concatenation of agetim e_high with agetime_low, multiplied by 1024 ms. for example, if agetime_low = 25 , and agetime_high = 01 (in hexadecimal), then the concatenated value 125 is equal to decimal 293. multiply ing 293 by 1024 ms, we determine that the corresponding aging time is 300 ms. in fact, 300 ms is the default aging time for the MDS105. the aging of all mct entries is checked once during each time period. if the mct entry has not been exercised before the end of the next time period, it will be deleted. 3.0 quality of service the MDS105 applies zarlink?s architecture to provide new quality of service (qos) capabilities for unmanaged switch applications. similar to the qos capabilities of other zarlink chipset memb ers, the MDS105 offers two transmit queues per output port. the frame engine (fe) manages the output transmission queues for all MDS105 ports. once the destination address search is complete, and the sw itch decision is sent back to the fe, the packet is inserted into the appropriate output queue. whether the packet is inserted in to a high or low priority queue is determined by either the vlan tag information or the type of service/differentiat ed services (tos/ds) field in the ip header. either of these priority fields can be used to select the transmi ssion priority (as per the use_tos bit in the fcr register).
MDS105 data sheet 8 zarlink semiconductor inc. the mapping of the priority field values into either th e high or low priority queue can be configured using the MDS105 configuration registers avpm and tospm. if the system uses the tos/ds field to prioritize packets, there are two choi ces regarding which bits of the tos/ds field are used. bits [0:2] of the tos byte (known as the ip precedence field) or bits [3:5] of the tos byte (known as the delay/throughput reliability (dtr) field) can be used to resolve the transmission queue priority. either bit group, [0:2] or [3:5], can also be used to resolve packet drop precedence, as per bits 6 and 7 of the register fcbst. the MDS105 utilizes weighted round robin (wrr) to schedule packets for transmission. to enable MDS105?s intelligent qos scheduling capab ilities, the use of an external eepr om to change the default register configurations is required. weighted round robin is an efficient method to ensure th at each of the transmission queues receives at least a minimum service level. with two output transmission que ues, the MDS105 will transmit x packets from the high priority queue before transmitting a single packet from the low priority queue. the MDS105 allows the designer to set the high priority weight x to a value between 1 and 15. if both queues contain packets, and the high priority weight is set to the value 4, then the MDS105 will tran smit 4 high priority packets before transmitting each low priority packet. the MDS105 also employs a proprietary mechanism to ensure the timely delivery of high priority packets. when the latency of high priority packets reaches a threshold, th e MDS105 will override the wrr weights and transmit only high priority packets until the high priority packet delays ar e below the threshold. this threshold limit is 1 ms (last-in- first-out). the MDS105?s proprietary scheduling algorithm is also designed to push low priority traffic through the device faster, if necessary, to unclog congested queues. loading the appropriate values into the configuration registers enables the qos scheduling capabilities of the MDS105. qos for packet transmission is enabled by performing the following four steps: 1. select the tos/ds or vlan priority tag field as th e decision-maker for ip packet scheduling. the selection is made using bit 7 of the flooding control register (fcr). - fcr[7] = 0: use vlan priority tag field to determine the transmission priority, if this tag field exists. - fcr[7] = 1: use tos/ds field fo r ip packet priority resolution. 2. select which tos/ds subfield to use as the decision-maker for packet transmission priority if the tos/ds field was selected in step 1. the selection is made using bit 6 of the fcb buffer low threshold register (fcbst). - fcbst[6] = 0: use dtr subfield to resolve the transmission priority. - fcbst[6] = 1: use ip precedence subfield 1 to resolve the transmission priority. 3. enable qos using bit 5 of the transmission schedulin g control register (axsc). set the transmission queue weight for the high priority queue using bits 0 to 3. 4. create the mapping from the value in the tos/ds or vlan priority tag field to the corresponding high or low priority output queue. the mapping is created using the vlan priority map (avpm) and tos priority map (tospm) registers. note that for half duplex operation, the priority queues 2 must be enabled using bit 7 in the transmission scheduling control (axsc) register to use qos scheduling. when qos and flow control are enabled, the MDS105 will utilize enhanced wrr to schedule packet transmission, and will use either back pressure or 802.3x flow control to handle buffer congestion. when qos is enabled and flow control is disabled, the MDS105 will utilize enhanced wrr to schedule packet transmission, and will use weighted random early detection/drop (wred) to drop random pa ckets in order to handle buffer congestion. because of wred, only a few packet flows are slowed down while the remaining see no impact from the network traffic congestion. 1. ip precedence and dtr subfields are referred to as tos/ds[0:2] and tos/ds[3:5] in the ip tos/ds byte. 2. in half duplex mode, qos schedul ing functions are disabled by default.
MDS105 data sheet 9 zarlink semiconductor inc. wred is a method of handling traffic congestion in the absence of flow control mechanisms 1 . when flow control is enabled, all devices that are connected to a switch node th at is exercising flow control are effectively unable to transmit, including nodes that are not directly responsibl e for the congestion problem. this inability to transmit during flow control periods would wreak havoc with voice packets, or other high priority packet flows, and therefore flow control is not recommended for networks that mix voice and data traffic. wred allows traffic to continue flowing into ports on a switch, and randomly drops packets with different probabilities based upon each packet?s priority markings. as the switch congestion increases, the probability of dropping an incoming packet increases, and as congestion decreases, the probability of dropping an incoming packet decreases. not surprisingly, packets designated high-drop are sacrificed with higher odds during congestion than packets designated low-drop. the following table summarizes the wred operation of the MDS105. it lists the buffer thresholds at which each drop probability takes effect. table 1 - wred operation of the MDS105 the wred packet drop capabilities of the MDS105 ar e enabled by performing the following four steps: 1. select the tos/ds or vlan tag field as the decision-maker for dropping packets. the selection is made using bit 7 of the flooding control register (fcr). - fcr[7] = 0: use vlan priority tag field to re solve the drop level, if this field exists. - fcr[7] = 1: use tos/ds field for ip packet drop level resolution. 2. select which tos/ds tag subfield to use for dropping pa ckets provided that the tos/ds field was selected in step 1. the selection is made using bit 7 of t he fcb buffer low threshold register (fcbst). - fcbst[7] = 0: use dtr subfield to resolve the drop precedence. - fcbst[7] = 1: use ip precedence subfield to resolve the drop precedence. 3. create the mapping from the values in the tos ds or vlan tag field to the packet flags representing high or low drop precedence. the mapping is created using the vlan discard map (avdm) and tos discard map (tosdm) registers. 4. make sure that the desired ports are flow control disabled, using the ecr1px registers. note that to apply the wred qos function of the MDS105, flow control must be disabled. 1. flow control, of course, provides the advantage of not dro pping packets. however, its primary disadvantage is that a flow co ntrolled port may experience head-of-line blocking. this means that if even 1 packet is destined to a congested output port, then all other packe ts originating from the same source may, in the worst case, be delayed ? even if these other packets have uncongested destinations. on the oth er hand, wred may cause some packet loss, but with no such head-of-line bl ocking problem. which method of handling traffic congestion sh ould be chosen will depend on the application. wred threshold drop percentage condition for high priority queue condition for low priority queue drop percentage for high-drop packet drop percentage for low-drop packet level 0 total buffer space available in device is lpbt 50% 0% level 1 24 buffers occupied 72 buffers occupied 75% 25% level 2 84 buffers occupied 100% 50%
MDS105 data sheet 10 zarlink semiconductor inc. 3.1 a few examples ? no qos scheduling desired at all . the default setting for the MDS105 is no qos scheduling at all. packets are transmitted using a simple first-in-first-out (fifo) approach, without the reordering that would result from prioritization. all destinations use 1 queue only. qos scheduling can be disabled for the entire chip using axsc[5]. ? no qos scheduling desired for half duplex ports . it is possible to disable qos for half duplex ports in the MDS105. indeed, this is the de fault setting, because it is difficult to assure quality of service for half duplex ports, which tend to experience unpredictable delay. all destinations configured as half duplex use 1 transmission queue only in this setting. qos scheduling can be disabled for all half duplex ports using axsc[7]. ? qos scheduling for some destinations, but not others . the MDS105 does not support this feature. the three options offered are: (a) all ports are qos-enabled, (b) no ports are qos-enabled, and (c) only full duplex ports are qos-enabled. of course, the MDS105 will still exhibit single-queue scheduling at a port if all packets destined for it are marked with a single transmission priority. ? no flow control desired . it is possible to disabl e flow control for the entire chip, regardless of the individual port settings. during congestion, some packets will be lost. this capability is located in axsc[6]. ? flow control desired for some sources, but not others . by configuring each port separately using bit 0 in the ecr1px registers, one may enable flow control for some ports, but not others. flow control cannot be globally disabled in axsc[6] if this function is to be achieved. at a congested destination, an incoming packet from a flow control enabled source will trigger a flow control message sent back to that source. on the other hand, an incoming packet from a flow control disabled source may or may not be dropped, as per wred, but will never trigger flow control. ? scheduling vs. dropping. using the configuration registers in the MDS105, as in earlier examples, a port may or may not have flow control enabled, and a port may or may not have qos scheduling enabled. all four combinations are permissible parameter settings, and which one is chosen depends on application. in one common application, suppose voice, critical data and web traffic packets originate from the same set of input ports, and are destined for the same set of output ports. the MDS105?s enhanced wrr scheduling can be used to ensure a delay bound for the voice packets. furthermore, because we want to guarantee that web traffic congestion does not block critical data or voice, we must disable flow control and use wred to intelligently drop packets. on the other hand, if the goal were file transfer with out any packet dropping, one would enable the MDS105?s flow control function, whic h halts incoming traffic when the system is congested. qos sch eduling can be disabled, both because flow control may make quality of service unpredicta ble, and because, in any case, delay is not critical in this application. 3.2 port-based prioritization some applications may require an explicit prioritization of packets based upon the port the packet originates from. defining specific ports of a switch to be ip phone ports is a specific example that makes use of MDS105?s ability to assign default priorities to ports. the MDS105 can be configured to provide specific priority definitions on up to two ports (ports 0 ? 1). these user defined port priorities override the packet priority markings (vlan tag or tos/ds), and the new priority is applied to all packets that enter the switch from that port. these po rt priority definitions are configured in the port priority (ptpri) register. there are two bits for each of the two ports that can support port-based priorities. the en bit allows the designer to turn on port priorities for each port, and the p bit allows the designer to select either high (1) or low (0) transmission priority for all packe ts that enter the switch through that port. when port priorities are enabled, the remaining ports will provide qos based upon the vlan tag or tos ds field mappings in the configuration registers. only those ports that have port prio rities enabled will override the priority mappings.
MDS105 data sheet 11 zarlink semiconductor inc. 4.0 buffer management the MDS105 stores each input packet into the external fr ame buffer memory while determining the destination the packet is to be forwarded to. the total number of packets that can be stored in the frame buffer memory depends upon the size of the external sbram that is utilized . for a 256 kb sbram the MDS105 can buffer 170 packets. for a 512 kb sbram the MDS105 can buffer 340 packets. in order to provide good quality of service characteristics, the MDS105 must carefully allocate the available buffer space. such careful allocation can be accomplished using the ex ternal eeprom to load the appropriate values into the MDS105 configuration registers. the low-drop prec edence buffer threshold (lpbt) register assures that traffic designated as low-drop actually receives reserv ed buffer space. the designer can set the minimum number of buffers reserved for low-drop unicast traffic, by setting this register with a value between 0 and 255. unreserved buffers are treated as shared, and are accessible to all types of incoming traffic. to set the maximum number of buffers permitted for all multicast packets, use the multicast buffer control register (mbcr). unlike the lpbt register, the mbcr register does not define a reserved area of buffer memory, but instead provides a bound on the number of multicas t packets that can be buffered at any one time. during operation the MDS105 will continuously monitor the amount of frame buffer memory that is available, and when the unused buffer space falls below a designer confi gurable threshold, the MDS105 will initiate flow control if enabled or wred if not. this threshold is set using the fcb buffer low threshold (fcbst) register. 5.0 virtual lans the MDS105 provides the designer the ability to define a single port-based virtual lan (vlan) for each of the five ports. this vlan is individually defined for each port using the port control registers (ecr1px[6:4]). bits [6:4] allow the designer to define a vlan id (value between 0 ? 3) for each port. when packets arrive at an input of the MDS105, the search engine will determine the vlan id for that port, and then determine which of the other ports are also members of that vlan by matching their assigned vlan id values. the packet will then be tran smitted to each port with the same vlan id as the source port. 6.0 port trunking port trunking allows the designer to configure the MDS105, such that ports 0 and 1 are defined as a single logical port. this provides a 200 mbps link to a switch or server utilizing two 100 mbps ports in parallel. ports 0 and 1 can be trunked by pulling the trunk_en pin to the high state. in this mode, the source mac addresses of all packets received from the trunk are checked against the mct database to ensure that they have a port id of 0 or 1. packets that have a port id othe r than 0 and 1 will cause the MDS105 to learn the new mac address for this port change. on transmission, the trunk port is determined by hashing the source and destination mac addresses. this provides a mapping between each mac address and an associated trunk port. subsequent packets with the same mac address will always utilize the same trunk port. the MDS105 also provides a safe fail-over mode for port trunking. if one of the two ports goes down, as identified by the port?s link status signal, then the MDS105 will switch all traffic over to the rema ining port in the trunk. thus, the trunk link is maintained, albeit at a lower effective bandwidth.
MDS105 data sheet 12 zarlink semiconductor inc. 7.0 port mirroring utilizing the 4 port mirroring control pins provides the ability to enable or disable port mirroring, select which of the remaining 3 ports is to be mirrored, and choose whether the receive or transmit data is being mirrored. the control for this function is shown in the following table. table 2 - port mirroring configuration when enabled, port mirroring will allow the user to monitor traffic going through the switch on output port 3. if the port mirroring control pins mir_ctl[3:0] are left floating , the MDS105 will operate with the port mirroring function disabled. when port mirroring is enabled, the user must configure port 3 to operate in the same mode as the port it is mirroring (autonegotiation, duplex, speed, flow control). 8.0 power saving mode in mac the MDS105 was designed to be power efficient. when the internal mac sections detect that the external port is not receiving or transmitting packets, it will shut off and conserve power. when new packet data is loaded into the output transmit fifo of a mac in power saving mode, th e mac will return to life and begin operating immediately. when the mac is in power saving mode and new packet data is received on the rmii, the mac will return to life and receive data normally into the receive fifo. this wakeup occurs when the mac sees the carrier sense data valid (crs_dv) signal asserted. using this method, the switch will turn off all mac sectio ns during periods when there is no network activity (at night, for example), and save power. for large networks this power savings could be large. to achieve the maximum power efficiency, the designer should use a physical layer transceiver that utilizes ?wake-on-lan? technology. 9.0 eeprom i 2 c interface a simple 2 wire serial interface is pr ovided to allow the configuration of the MDS105 from an external eeprom. the MDS105 utilizes a 1 k bit eeprom with an i 2 c interface. mirrored port mirror_control [3] mirror_control [2] mirror_control [1] mirror_control [0] port 0 rx 1 0 0 0 port 0 tx 0 0 0 0 port 1 rx 1 0 0 1 port 1 tx 0 0 0 1 port 2 rx 1 1 1 0 port 2 tx 0 1 1 0 disabled 0/1 1 1 1
MDS105 data sheet 13 zarlink semiconductor inc. 10.0 management interface the MDS105 uses a standard parallel port interface to provide external cpu access to the internal registers. this parallel interface is composed of 3 pins: data0, strobe, and ack. the data0 pin provides the address and data content input to the MDS105, while the ack pin provides the corresponding output to the external cpu. the strobe pin is provided as the clock for both serial data streams. any of the MDS105 internal registers can be modified through this pa rallel port interface 1 . figure 3 - write command figure 4 - read command each management interface transfer consists of four parts: 1. a start pulse ? occurs when data is sampled high when strobe is rising followed by data being sampled low when strobe falls. 2. register address strobed into data0 pin, using the high level of the strobe pin. 3. either a read or write command (see waveforms above). 4. data to be written provided on data0, or data to be read provided on ack. any command can be aborted in the middle by sending an abort pulse to the MDS105. an abort pulse occurs when data is sampled low and strobe is rising, followed by data being sampled high when strobe falls. 1. the 3-bit parallel interface is not ?parallel? in the usual se nse of the word; it is actually a synchronous serial architect ure. however, the MDS105 management interface adheres to ieee 1284 parallel port standards.
MDS105 data sheet 14 zarlink semiconductor inc. 11.0 configuration register definitions the MDS105 registers can be accessed via the parallel interface and/or the i 2 c interface. some registers are only accessible through the parallel interface. the access method for each register is listed in the individual register definitions. each register is 8 bits wide. 11.1 gcr - global control register ? access: parallel interface, write only ? address: h30 11.2 dcr - device status and signature register ? access: parallel interface, read only ? address: h31 bit 0 save configuration into eeprom write '1' followed by a '0' (default = 0) bit 1 save configuration into eepr om and reset system write '1' (self-clearing due to reset) (default = 0) bit 2 start built-in self-test (bist) write '1' followed by a '0' (default = 0) bit 3 reset system write '1' (self-clearing due to reset) (default = 0) bit [7:4] reserved bit 0 busy writing configuration from i 2 c 1: activity 0: no activity bit 1 busy reading configuration from i 2 c 1: activity 0: no activity bit 2 built-in self-test (bist) in progress 1: bist in-progress 0: normal mode bit 3 ram error during bist 1: ram error 0: no error bits [5:4] reserved bits [7:6] revision number 00: initial silicon 01: second silicon
MDS105 data sheet 15 zarlink semiconductor inc. 11.3 da ? da register ? access: parallel interface, read only ? address: h36 returns 8 bit value da (hexadecimal) if the parallel port connection is good. otherwise, returns some other value indicating failure. 11.4 mbcr ? multicast buffer control register ? access: parallel interface and i 2 c, read/write ? address: h00 11.5 fcbst ? fcb buffer low threshold ? access: parallel interface and i 2 c, read/write ? address: h01 11.6 lpbt ? low drop precedence buffer threshold ? access: parallel interface and i 2 c, read/write ? address: h02 bit [7:0] max_cnt_lmt maximum number of multicast frames allowed to be buffered inside the device at any one time (default = 80) bits [5:0] buf_low_th buffer low threshold ? the number of free buffers below which flow control or wred is triggered (default = 3f) bit 6 use ip precedence subfield (tos[0:2]) for transmission priority (default = 0) bit 7 use ip precedence subfield (tos[0:2]) for drop level (default = 0) note that, for bits 6 and 7, default = 0 means to use tos[3:5]. bits [7:0] low_drop_cnt number of frame buffers reserved for low-drop traffic (default 3f)
MDS105 data sheet 16 zarlink semiconductor inc. 11.7 fcr ? flooding control register ? access: parallel interface and i 2 c, read/write ? address: h03 11.8 avtcl ? vlan type code register low ? access: parallel interface and i 2 c, read/write ? address: h04 11.9 avtch ? vlan type code register high ? access: parallel interface and i 2 c, read/write ? address: h05 11.10 avpm ? vlan priority map ? access: parallel interface and i 2 c, read/write ? address: h06 bits [3:0] u2mr maximum number of flooded frames allowed within any time interval indicated by timebase bits (violations are discarded) (default = 8) bits [6:4] timebase 000 = 100 s 001 = 200 s 010 = 400 s 011 = 800 s 100 = 1.6 s 101 = 3.2 s 110 = 6.4 s 111 = 100 s (default = 000) bit 7 use_tos use tos instead of vlan priority for ip packet (default = 0) bit [7:0] vlantype_low lower 8 bits of vlan type code (default = 00) bit [7:0] vlantype_high upper 8 bits of vlan type code (default 81) map vlan tag into 2 transmit queues (0 = low priority, 1 = high priority) bit 0 mapped priority of tag value 0 (default 0) bit 1 mapped priority of tag value 1 (default 0) bit 2 mapped priority of tag value 2 (default 0) bit 3 mapped priority of tag value 3 (default 0) bit 4 mapped priority of tag value 4 (default 0) bit 5 mapped priority of tag value 5 (default 0) bit 6 mapped priority of tag value 6 (default 0) bit 7 mapped priority of tag value 7 (default 0)
MDS105 data sheet 17 zarlink semiconductor inc. 11.11 avdm ? vlan discard map ? access: parallel interface and i 2 c, read/write ? address: h07 11.12 tospm ? tos priority map ? access: parallel interface and i 2 c, read/write ? address: h08 11.13 ptpri ? port priority ? access: parallel interface and i 2 c, read/write ? address: h09 map vlan tag into frame discard levels (0 = low drop, 1 = high drop). bit 0 frame discard for tag value 0 (default 0) bit 1 frame discard for tag value 1 (default 0) bit 2 frame discard for tag value 2 (default 0) bit 3 frame discard for tag value 3 (default 0) bit 4 frame discard for tag value 4 (default 0) bit 5 frame discard for tag value 5 (default 0) bit 6 frame discard for tag value 6 (default 0) bit 7 frame discard for tag value 7 (default 0) map tos field in ip packet into 2 transmit queues (0 = low priority, 1 = high priority). bit 0 mapped priority when tos is 0 (default 0) bit 1 mapped priority when tos is 1 1 1. tos = 1 means the appropriate 3 bit tos subfield is ?001. (default 0) bit 2 mapped priority when tos is 2 (default 0) bit 3 mapped priority when tos is 3 (default 0) bit 4 mapped priority when tos is 4 (default 0) bit 5 mapped priority when tos is 5 (default 0) bit 6 mapped priority when tos is 6 (default 0) bit 7 mapped priority when tos is 7 (default 0) enable and configure port-based priorities for ports 0, and 1 bit 0 en0 port 0: enable; 1 = enabled (default 0) bit 1 p0 port 0: priority; 1 = high, 0 = low (default 0) bit 2 en1 port 1: enable; 1 = enabled (default 0) bit 3 p0 port 1: priority; 1 = high, 0 = low (default 0) bit 7:4 reserved
MDS105 data sheet 18 zarlink semiconductor inc. 11.14 tosdm ? tos discard map ? access: parallel interface and i 2 c, read/write ? address: h0a 11.15 axsc ? transmission scheduling control register ? access: parallel interface and i 2 c, read/write ? address: h0b 11.16 mii_op0 ? mii register option 0 ? access by parallel interface and i 2 c, read/write ? address: h0c map tos into frame discard levels (0 = low-drop, 1 = high-drop). bit 0 frame discard when tos is 0 (default 0) bit 1 frame discard when tos is 1 (default 0) bit 2 frame discard when tos is 2 (default 0) bit 3 frame discard when tos is 3 (default 0) bit 4 frame discard when tos is 4 (default 0) bit 5 frame discard when tos is 5 (default 0) bit 6 frame discard when tos is 6 (default 0) bit 7 frame discard when tos is 7 (default 0) bits [3:0] transmission queu e service weight for high priority queue (default f) bit [5] global quality of service enable (default 0) bit [6] global flow control disable ? if 1, flow control is disabled globally; if 0, each port?s flow control settings are separately configurable (default 0) bit [7] half duplex priority en able ? if 0, priority is disabled for all half duplex ports; if 1, priority is enabled unless axsc[5] = 0 (default 0) permits a non-standard address for the phy status register. when low and high address bytes are 0, the mds108 will use the standard address. bit [7:0] low order address byte (default 00)
MDS105 data sheet 19 zarlink semiconductor inc. 11.17 mii_op1 ? mii register option 1 ? access: parallel interface and i 2 c, read/write ? address: h0d 11.18 agetime_low ? mac address aging timer low ? access: parallel interface and i 2 c, read/write ? address: h0e 11.19 agetime_high ? mac address aging timer high ? access: parallel interface and i 2 c, read/write ? address: h0f 11.20 ecr1p0 ? port 0 control register ? access: parallel interface and i 2 c, read/write ? address: h10 bit [7:0] high order address byte (default 00) bit [7:0] low byte of the mac address aging timer (default 25) bit [7:0] high byte of the mac address aging timer. the aging time is based on the follow ing formula: {agetime_high, agetime_low} x 1024 ms (default 01) the default setting provides a 300 second aging time. bits [3:0] port mode (default 0000) bit [3] 1 ? force configuration based on bits [2:0] 0 ? autonegotiate and advertise based on bits [2:0] bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [1] 1 ? half duplex 0 ? full duplex bit [0] 1 ? flow control off 0 ? flow control on bits [6:4] pvid port-based vlan id (default 000) bit [7] reserved
MDS105 data sheet 20 zarlink semiconductor inc. 11.21 ecr1p1 ? port 1 control register ? access: parallel interface and i 2 c, read/write ? address: h11 11.22 ecr1p2 ? port 2 control register ? access: parallel interface and i 2 c, read/write ? address: h12 11.23 ecr1p3 ? port 3 control register ? access: parallel interface and i 2 c, read/write ? address: h13 bits [3:0] port mode (default 0000) bit [3] 1 ? force configuration based on bits [2:0] 0 ? autonegotiate and advertise based on bits [2:0] bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [1] 1 ? half duplex 0 ? full duplex bit [0] 1 ? flow control off 0 ? flow control on bits [6:4] pvid port-base d vlan id (default 000) bit [7] reserved bits [3:0] port mode (default 0000) bit [3] 1 ? force configuration based on bits [2:0] 0 ? autonegotiate and advertise based on bits [2:0] bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [1] 1 ? half duplex 0 ? full duplex bit [0] 1 ? flow control off 0 ? flow control on bits [6:4] pvid port-base d vlan id (default 000) bit [7] reserved bits [3:0] port mode (default 0000)
MDS105 data sheet 21 zarlink semiconductor inc. 11.24 ecr1p4 ? port 4 control register ? access: parallel interface and i 2 c, read/write ? address: h14 11.25 fc_0 ? flow control byte 0 ? access: parallel interface and i 2 c, read/write ? address: h19 the flow control hold time parameter is the length of time a flow control message is effectual (i.e. halts incoming traffic) after being received. the hold time is measured in units of ?slots,? the time it takes to transmit 64 bytes at wire-speed. the default setting is 32 slots, or for a 100 mbps port, approximately 164 ms. bits [7:0] flow control hold time byte 0 (default ff) bit [3] 1 ? force configuration based on bits [2:0] 0 ? autonegotiate and advertise based on bits [2:0] bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [1] 1 ? half duplex 0 ? full duplex bit [0] 1 ? flow control off 0 ? flow control on bits [6:4] pvid port-base d vlan id (default 000) bit [7] reserved bits [3:0] port mode (default 0000) bit [3] 1 ? force configuration based on bits [2:0] 0 ? autonegotiate and advertise based on bits [2:0] bit [2] 1 ? 10 mbps 0 ? 100 mbps bit [1] 1 ? half duplex 0 ? full duplex bit [0] 1 ? flow control off 0 ? flow control on bits [6:4] pvid port-base d vlan id (default 000) bit [7] reserved
MDS105 data sheet 22 zarlink semiconductor inc. 11.26 fc_1 ? flow control byte 1 ? access: parallel interface and i 2 c, read/write ? address: h1a bits [7:0] flow control hold time byte 1 (default 00) 11.27 fc_2 ? flow control crc byte 0 ? access: parallel interface and i 2 c, read/write ? address: h1b bits [7:0] flow control frame crc byte 0 (default 96) 11.28 fc_3 ? flow control crc byte 1 ? access: parallel interface and i 2 c, read/write ? address: h1c bits [7:0] flow control frame crc byte 1 (default 8e) 11.29 fc_4 ? flow control crc byte 2 ? access: parallel interface and i 2 c, read/write ? address: h1d bits [7:0] flow control frame crc byte 2 (default 99) 11.30 fc_5 ? flow control crc byte 3 ? access: parallel interface and i 2 c, read/write ? address: h1e bits [7:0] flow control frame crc byte 3 (default 9a) 11.31 checksum - eeprom checksum ? access: parallel interface and i 2 c, read/write ? address: h24 the calculation is [0x100 - ((sum of registers 0x00~ 0x23) & 0xff)]. for example, based on the default register settings, the checksum value would be 0xee. bits [7:0] che cksum (default 00)
MDS105 data sheet 23 zarlink semiconductor inc. 12.0 MDS105 pin descriptions note: # active low signal i input signal s input signal with schmitt-trigger o output signal od open-drain driver i/o input & output signal sl slew rate controlled d pulldown u pullup 5 5 v tolerance pin no(s). symbol type name & functions frame buffer memory interface 201, 200, 199, 197, 196, 195, 193, 192, 191, 190, 188, 187, 186, 185, 183, 182, 181, 179, 178, 177, 176, 174, 173, 172, 170, 169, 168, 167, 165, 164, 163, 161 l_d[31:0] i/o, u, sl databus to frame buffer memory 203, 151, 158, 160, 10, 9, 8, 6, 5, 4, 2, 1, 208, 206, 205, 204, 150 l_a[18:2] i/o, u, sl address pins for buffer memory 153 l_clk o frame buffer memory clock 155 l_we# o, sl frame buffer memory write enable 156 l_oe# o frame buffer memory output enable 157 l_adsc# o, sl frame buffer memory address status control mii management interface 120 m_mdc o mii management data clock 122 m_mdio i/o, u mii management data i/o i 2 c interface (seria l eeprom interface) 123 scl o, u, 5 i 2 c data clock 124 sda i/o, u, od, 5 i 2 c data i/o parallel port management interface 127 strobe i, u, s, 5 strobe pin 128 data0 i, u, 5 data pin 129 ack o, u, od, 5 acknowledge pin port 0 rmii interface 24, 23 m0_rxd[1:0] i, u port 0 receive data 22 m0_crs_dv i, d port 0 carrier sense and data valid 21, 20 m0_txd[1:0] o port 0 transmit data 19 m0_txen o port 0 transmit enable port 1 rmii interface 31, 30 m1_rxd[1:0] i, u port 1 receive data
MDS105 data sheet 24 zarlink semiconductor inc. 29 m1_crs_dv i, d port 1 carrier sense and data valid 28, 27 m1_txd[1:0] o port 1 transmit data 26 m1_txen o port 1 transmit enable port 2 rmii interface 79, 78 m2_rxd[1:0] i, u port 2 receive data 77 m2_crs_dv i, d port 2 carrier sense and data valid 76, 75 m2_txd[1:0] o port 2 transmit data 74 m2_txen o port 2 transmit enable port 3 rmii interface 86, 85 m3_rxd[1:0] i, u port 3 receive data 84 m3_crs_dv i, d port 3 carrier sense and data valid 83, 82 m3_txd[1:0] o port 3 transmit data 81 m3_txen o port 3 transmit enable port 4 mii interface 105, 104, 103, 102 m4_rxd[3:0] i, u port 4 receive data 113, 112, 111, 110 m4_txd[3;0] o port 4 transmit data 109 m4_txen o port 4 transmit enable 97 m4_rxdv i, d port 4 receive data valid 100 m4_rxclk i, u port 4 receive clock 107 m4_txclk i/o, u port 4 transmit clock 114 m4_link i, u port 4 link status 116 m4_speed i/o, u port 4 speed select (100 mb = 1) 115 m4_duplex i, u port 4 full-duplex select (half-duplex = 0) 98 m4_col i, u port 4 collision detect port 4 serial interface 102 s4_rxd i, u port 4 serial receive data 100 s4_rxclk i, u port 4 serial receive clock 97 s4_crs_dv i, d port 4 serial carrier sense and data valid 110 s4_txd o port 4 serial transmit data 107 s4_txclk i port 4 serial transmit clock 109 s4_txen o port 4 serial transmit enable 98 s4_col i, u port 4 serial collision detect 114 s4_link i, u port 4 link status 115 s4_duplex i, u port 4 full-duplex select (half-duplex = 0) miscellaneous control pins 95 m_clk i reference rmii clock 118 m4_refclk o, u port 4 reference clock (m_clk/2) 148 sclk i system clock (25 - 50 mhz) 125 test# i, u manufacturing pin leave as no connect (nc) pin no(s). symbol type name & functions
MDS105 data sheet 25 zarlink semiconductor inc. 126 trunk_en i, d port trunking enable 146, 145, 144, 143 mir_ctl[3:0] i/o, u port mirroring control 142 resin# i, s reset pin 141 resetout# o phy reset pin test pins 139 tmode# i/o, u manufacturing pin. pu ts device into test mode for ate test. leave as no connect (nc). 138, 137, 136, 135 tstout[7:4] o test outputs 134, 133, 132, 131 tstout[3:0] i/o, u test outputs nc pins 12, 13, 14, 15, 16, 17, 33, 34, 35, 36, 37, 38, 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 60, 61, 62, 63, 64, 65, 67, 68, 69, 70, 71, 72, 88, 89, 90, 91, 92, 93 n/c reserved no connect power pins 3, 39, 73, 96, 130, 159, 184 vdd (core) input +3.3 volt dc supply for core logic (7 pins) 11, 25, 59, 87, 101, 108, 119, 147, 152, 166, 175, 194, 202 vdd input +3.3 volt dc supply for i/o pads (13 pins) 18, 46, 80, 106, 140, 171, 198 vss (core) input gro und for core lo gic (7 pins) 7, 32, 66, 94, 99, 117, 121, 149, 154, 162, 180, 189, 207 vss input ground for i/o pads (13 pins) pin no(s). symbol type name & functions
MDS105 data sheet 26 zarlink semiconductor inc. 12.1 strap options the strap options are relevant during the initial power-on period, when reset is assert ed. during reset, the MDS105 will examine the boot strap address pin to determine its va lue and modify the internal configuration of the chip accordingly. ?1? means pull-up ?0? means pull-down with an external 1 k ohm default value is 1, (all boot strap pins have internal pull-up resistor). 1. if the MDS105 is configured from eeprom preset (l_a[6] pulled do wn at reset), it will try to load its configuration from the eeprom. if the eeprom is blank or not preset, it will not boot up. the pa rallel port can be used to program the eeprom at any time. 2. during normal power-up, the MDS105 will run through an external sbram memory test to ensure that there are no memory interfa ce prob- lems. if a problem is detected, the chip will stop functioning. to facilitate board d ebug in the event that a system stops func tioning, the msd105 can be put into a continuous sbram self test mode to allow an operator to determine if there are stuck pins in the memor y interface (using network analyzer). pin no(s). symbol name & functions boot strap pins 206 (l_a[5]) memory size 1 - memory size = 256 kb 0 - memory size = 512 kb 208 (l_a [6]) eeprom 1 - no eeprom installed 0 - eeprom installed 1 151 (l_a[17]) port 4 mii/seri al 1 - mii mode for port 4 0 - serial mode for port 4 150 (l_a[2]) link polarity link polarity for serial interface 1 - active low 0 - active high 204 (l_a[3]) fdx polarity full/half duplex polarity for serial interface 1 - active low 0 - active high 205 (l_a[4]) spd100 polarity speed polarity for serial interface 1 - active low 0 - active high 133 (tst[2]) sbram self test for board/system manufacturing test 2 1 - disable 0 - enable
MDS105 data sheet 27 zarlink semiconductor inc. 13.0 characteristics and timing 13.1 absolute maximum rating storage temperature -65 c to +150 c operating temperature -40 c to +85 c maximum junction temperature +125 c supply voltage vdd with respect to v ss +3.0 v to +3.6 v voltage on 5v tolerant input pins -0.5 v to (vdd +3.3 v) voltage on other pins -0.5 v to (vdd +0.3 v) caution: stresses above those listed may cause permanent device failure. functionality at or above these limits is not implied. exposure to the absolute maximum ratings for extended ratings for extended periods may affect device reliability. 13.2 dc electrical characteristics vdd = 3.0 v to 3.6 v (3.3v +/- 10%) t ambient = -40 c to +85 c 13.3 recommended operating conditions symbol parameter description min. typ. max. unit f osc frequency of operation 25 50 80 mhz i dd v oh v ol supply current - @ 50 mhz (vdd = 3.3 v) tbd ma output high voltage (cmos) 2.4 v output low voltage (cmos) 0.4 v v ih - ttl input high voltage (ttl 5 v tolerant) 2.0 vdd + 2.0 v v il - ttl input low voltage (ttl 5 v tolerant) 0.8 v i il input leakage current (0.1 v < v in < vdd) (all pins except those with internal pull-up/ pull- down resistors) 10 a i ol output leakage current (0.1 v < v out < vdd) 10 a c in input capacitance 5 pf c out output capacitance 5 pf c i/o i/o capacitance 7 pf ja thermal resistance wi th 0 air flow 29.7 c/w ja thermal resistance with 1 m/s air flow 28.8 c/w ja thermal resistance with 2 m/s air flow 26.8 c/w jc thermal resistance between junction and case 12.6 c/w
MDS105 data sheet 28 zarlink semiconductor inc. 13.4 clock frequency specifications suggestion clock rate for various configurations: symbol parameter (hz) note: c1 sclk - core system clock input 50 m c2 m_clk - rmii port clock 50 m c3 m4_refclk - mii reference clock 25 m c4 l_clk - frame buffer memory clock 50 m l_clk = sclk c5 m_mdc - mii management data clock 1.56 m m_mdc = sclk/32 c6 scl - i 2 c data clock 50 k scl = m_clk/1000 input output configuration sclk m_clk (rmii) l_clk m_mdc scl port 0-3 port 4 10 m rmii 10/100 m mii 25 m 50 m =sclk =sclk/32 50 k 100 m rmii not used 50 m 50 m =sclk =sclk/32 50 k 100 m rmii 10/100 m mii 50 m 50 m =sclk =sclk/32 50 k
MDS105 data sheet 29 zarlink semiconductor inc. 14.0 ac timing characteristics 14.1 frame buffer memory interface: figure 5 - frame buffer memory interface timing symbol parameter 50 mhz note min. (ns) max. (ns) l1 l_d[31:0] input setup time 5 l2 l_d[31:0] input hold time 0 l3 l_d[31:0] output valid delay 1 8 c l = 30 pf l4 l_a[18:2] output valid delay 1 8 c l = 50 pf l6 l_adsc# output valid delay 1 8 c l = 50 pf l8 l_we# output valid delay 1 8 c l = 30 pf l9 l_oe# output valid delay 1 8 c l = 30 pf table 3 - frame buffer memory interface timin l_d[31:0]
MDS105 data sheet 30 zarlink semiconductor inc. 14.2 rmii timing requirements 14.3 mii timing requirements figure 6 - transmit timing *inf. - infinite table 5 - transmit timing requirements symbol parameter 50 mhz note min. (ns) max. (ns) m1 m_clk reference input clock m2 m[3:0]_rxd[1:0] input setup time 4 m3 m[3:0]_rxd[1:0] input hold time 1 m4 m[3:0]_crs_dv input setup time 4 m5 m[3:0]_txen output delay time 1 11 c l = 30 pf m6 m[3:0]_txd[1:0] output delay time 1 11 c l = 30 pf m7 m[3:0]_link input setup time 4 table 4 - rmii timing requirements symbol parameter time unit min. max. 1 m4_txclk rise to m4_txd [3:0] inactive delay 5 20 ns 2 m4_txclk rise to m4_txd [3:0] active delay 5 20 ns 3 m4_txclk rise to m4_txen active delay 5 20 ns 4 m4_txclk rise of last m4_txd bit to m4_txen inactive delay 520ns 5 m4_txclk high wide 25 inf. ns 6 m4_txclk low wide 25 inf. ns m4_txclk input rise time require 5 ns m4_txclk input fall time require 5 ns
MDS105 data sheet 31 zarlink semiconductor inc. figure 7 - receive timing *inf. - infinite table 6 - receive timing requirements symbol parameter time unit min. max. 1 m4_rxd[3:0] low input setup time 10 ns 2 m4_rxd[3:0] low input hold time 5 ns 3 m4_rxd[3:0] high input setup time 10 ns 4 m4_rxd[3:0] high input hold time 5 ns 5 m4_rxdv low input setup time 10 ns 6 m4_rxdv low input hold time 5 ns 7 m4_rxdv high input setup time 10 ns 8 m4_rxdv high input hold time 5 ns 9 m4_rxclk high wide 25 inf. ns 10 m4_rxclk low wide 25 inf. ns m4_rxclk input rise time require 5 ns m4_rxclk input fall time require 5 ns m4_rxclk m4_rxd[3:0] m4_rxdv
MDS105 data sheet 32 zarlink semiconductor inc. 14.4 port 4 serial mode ac timing figure 8 - transmit timing *inf. - infinite table 7 - transmit timing requirements symbol parameter time unit min. max. 1 s4_txclk rise to s4_txd inactive delay 5 20 ns 2 s4_txclk rise to s4_txd active delay 5 20 ns 3 s4_txclk rise to s4_txen active delay 5 20 ns 4 s4_txclk rise of last s4_txd bit to s4_txen inactive delay 520ns 5 s4_txclk high wide 25 inf. ns 6 s4_txclk low wide 25 inf. ns s4_txclk input rise time require 5 ns s4_txclk input fall time require 5 ns
MDS105 data sheet 33 zarlink semiconductor inc. figure 9 - receive timing *inf. - infinite table 8 - receive timing requirements symbol parameter time unit min. max. 1 s4_rxd low input setup time 10 ns 2 s4_rxd low input hold time 5 ns 3 s4_rxd high input setup time 10 ns 4 s4_rxd high input hold time 5 ns 5 s4_crs_dv low input setup time 10 ns 6 s4_crs_dv low input hold time 5 ns 7 s4_crs_dv high input setup time 10 ns 8 s4_crs_dv high input hold time 5 ns 9 s4_rxclk hi wide 25 inf. ns 10 s4_rxclk low wide 25 inf. ns s4_rxclk input rise time require 5 ns s4_rxclk input fall time require 5 ns
c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes: 3. the top package body size may be smaller than the bottom package body size by a max. of 0.15 mm. 1. pin 1 indicator may be a corner chamfer, dot or both. 2. controlling dimensions are in millimeters. 4. dimension d1 and e1 do not include mould protusion. notes: pin 1 index corner e1 e d d1 l a1 a2 a = 0-7
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